Материал: DOC1228

ATmega161(L)

Fill the Temporary Buffer

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“0001” to SPMCR, and execute SPM within four clock cycles after writing SPMCR. The

content of Z6:Z1 is used to address the data in the temporary buffer. Z13:Z7 must point

to the page that is supposed to be written.

Perform a Page Write

To execute a page write, set up the address in the Z-pointer, write “0101” to SPMCR,

and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0

are ignored. The page address must be written to Z13:Z7. During this operation, Z6:Z0

must be zero to ensure that the page is written correctly. When a page write operation is

completed, the Z-pointer will point to the first word in the successive page.

Code Example

Wait:

in

r16,SPMCR ; read SPMCR register

sbrc

r16,SPMEN

; Wait for SPMEN to be cleared (indicates that previous

write operation is completed)

rjmp

Wait

; if not cleared, keep waiting

ldi

r16,(1<<PGWRT) + (1<<SPMEN)

; The previous writing is completed,

set up for next erase

out

SPMCR,r16

; output to register

spm

; start the erase operation

Addressing the FLASH during

The Z-pointer is used to address the SPM commands.

Self-programming

Bit

15

14

13

12

11

10

9

8

$1F ($1F)

Z15

Z14

Z13

Z12

Z11

Z10

Z9

Z8

ZH

$1E ($1E)

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

ZL

7

6

5

4

3

2

1

0

Z15:Z14

always ignored

Z13:Z7 page select, for page erase, page write

Z6:Z1

word select, for filling temp buffer (must be zero during page write operation)

Z0

should be zero for all SPM commands, byte select for the LPM instruction

Store Program Memory

The Store Program Memory Control Register contains the control bits needed to control

Control Register – SPMCR

the programming of the Flash from internal code execution.

Bit

7

6

5

4

3

2

1

0

$37 ($57)

–

–

BLBSET

PGWRT

PGERS

SPMEN

SPMCR

Read/Write

R

R

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega161 and always read as zero.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Boot Lock bits according to the data in R0. The data in R1 and the address

in the Z-pointer are ignored. The BLBSET bit will auto-clear upon completion of Lock bit

set, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing Lock bit setting. Only a chip erase can clear the Lock bits.

An LPM instruction within four cycles after BLBSET and SPMEN are set in the SPMCR

register will put either the Lock bits or the Fuse bits (depending od the Z0 in the Z-

pointer) into the destination register. See “Reading the Fuse and Lock Bits from Soft-

ware” for details.

• Bit 2 – PGWRT: Page Write

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock

cycles executes page write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.

The PGWRT bit will auto-clear upon completion of a page write or if no SPM instruction

is executed within four clock cycles. The CPU is halted during the entire page write

operation.

• Bit 1 – PGERS: Page Erase

If this bit is set at the same time as SPMEN, the next SPM instruction within four clock

cycles executes a page erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon comple-

tion of a page erase or if no SPM instruction is executed within four clock cycles. The

CPU is halted during the entire page erase operation.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If set together with

either BLBSET, PGWRT or PGERS, the following SPM instruction will have a special

meaning (see description above). If only SPMEN is set, the following SPM instruction

will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of

an SPM instruction or if no SPM instruction is executed within four clock cycles.

Writing any combination other than “1001”, “0101”, “0011” or “0001” in the lower four

bits, or writing to the I/O register when any bits are set, will have no effect.

EEPROM Write Prevents

Note that an EEPROM write operation will block all software programming to Flash.

Writing to SPMCR

Reading the Fuse and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user check the status bit (EEWE)

in the EECR register and verify that the bit is cleared before writing to the SPMCR

register.