The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit codings are shown in Table 43.
When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions as shown in Table 44.
Figure 76. Parallel Programming
ATmega161
+5V
RDY/BSY
PD1
VCC
OE
PD2
PB7 - PB0 
DATA
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
RESET
PA0
XTAL1
GND
Table 42. Pin Name Mapping
Signal Name in |
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Programming Mode |
Pin Name |
I/O |
Function |
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PD1 |
O |
0: Device is busy programming; 1: Device is ready |
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for new command |
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PD2 |
I |
Output Enable (Active low) |
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OE |
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PD3 |
I |
Write Pulse (Active low) |
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WR |
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BS1 |
PD4 |
I |
Byte Select 1 (“0” selects low byte, “1” selects |
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high byte) |
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XA0 |
PD5 |
I |
XTAL Action Bit 0 |
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XA1 |
PD6 |
I |
XTAL Action Bit 1 |
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PAGEL |
PD7 |
I |
Program Memory Page Load |
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BS2 |
PA0 |
I |
Byte Select 2 (Always low) |
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DATA |
PB7 - 0 |
I/O |
Bi-directional Data Bus (Output when |
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OE is low) |
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116 ATmega161(L)
1228B–09/01
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ATmega161(L) |
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Table 43. XA1 and XA0 Coding |
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XA1 |
XA0 |
Action when XTAL1 is Pulsed |
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0 |
0 |
Load Flash or EEPROM Address (High or low address byte determined by BS1) |
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0 |
1 |
Load Data (High or low data byte for Flash determined by BS1) |
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1 |
0 |
Load Command |
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1 |
1 |
No Action, Idle |
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Table 44. Command Byte Bit Coding
Command Byte |
Command Executed |
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1000 0000 |
Chip Erase |
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0100 0000 |
Write Fuse Bits |
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0010 0000 |
Write Lock Bits |
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0001 0000 |
Write Flash |
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0001 0001 |
Write EEPROM |
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0000 1000 |
Read Signature Bytes |
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0000 0100 |
Read Fuse and Lock Bits |
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0000 0010 |
Read Flash |
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0000 0011 |
Read EEPROM |
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Enter Programming Mode |
The following algorithm puts the device in parallel programming mode: |
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1. |
Apply 4.5 - 5.5V between VCC and GND. |
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Set |
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and BS pins to “0” and wait at least 500 ns. |
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RESET |
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Apply 11.5 - 12.5V to |
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RESET, |
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Chip Erase |
The Chip Erase will erase the Flash and EEPROM memories plus Lock bits. The Lock |
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Load Command “Chip Erase” |
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Set XA1, XA0 to “10”. This enables command loading. |
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Set BS1 to “0”. |
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Set DATA to “1000 0000”. This is the command for Chip Erase. |
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Give |
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goes low. |
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WR |
a negative pulse. This starts the Chip Erase. RDY/BSY |
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5. |
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goes high before loading a new command. |
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Wait until RDY/BSY |
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Programming the Flash |
The Flash is organized as 128 pages of 128 bytes each. When programming the Flash, |
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the program data is latched into a page buffer. This allows one page of program data to |
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be programmed simultaneously. The following procedure describes how to program the |
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entire Flash memory: |
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A. Load Command “Write Flash”
1.Set XA1, XA0 to “10”. This enables command loading.
2.Set BS1 to “0”.
3.Set DATA to “0001 0000”. This is the command for Write Flash.
4.Give XTAL1 a positive pulse. This loads the command.
117
1228B–09/01
B. Load Address Low Byte
1.Set XA1, XA0 to “00”. This enables address loading.
2.Set BS1 to “0”. This selects low address.
3.Set DATA = Address low byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1.Set BS1 to “0”. This selects low data byte.
2.Set XA1, XA0 to “01”. This enables data loading.
3.Set DATA = Data low byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the data byte.
D. Latch Data Low Byte
Give PAGEL a positive pulse. This latches the data low byte. (See Figure 77 for signal waveforms.)
E. Load Data High Byte
1.Set BS1 to “1”. This selects high data byte.
2.Set XA1, XA0 to “01”. This enables data loading.
3.Set DATA = Data high byte ($00 - $FF).
4.Give XTAL1 a positive pulse. This loads the data byte.
F. Latch Data High Byte
Give PAGEL a positive pulse. This latches the data high byte.
G. Repeat “B” through “F” 64 times to fill the page buffer.
To address a page in the Flash, seven bits are needed (128 pages). The five most significant bits are read from address high byte as described in section “H” below. The two least significant page address bits, however, are the two most significant bits (bit7 and bit6) of the latest loaded address low byte as described in section “B”.
H. Load Address High byte
1.Set XA1, XA0 to “00”. This enables address loading.
2.Set BS1 to “1”. This selects high address.
3.Set DATA = Address high byte ($00 - $1F).
4.Give XTAL1 a positive pulse. This loads the address high byte.
I. Program Page
1.Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSYgoes low.
2.Wait until RDY/BSY goes high.
(See Figure 78 for signal waveforms.)
J. End Page Programming
1.Set XA1, XA0 to “10”. This enables command loading.
2.Set DATA to “0000 0000”. This is the command for No Operation.
3.Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
K. Repeat “A” through “J” 128 times or until all data have been programmed.
118 ATmega161(L)
1228B–09/01
ATmega161(L)
Figure 77. Programming the Flash Waveforms
DATA |
$10 |
ADDR. LOW |
ADDR. HIGH |
DATA LOW |
XA1
XA2
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
BS2
PAGEL
Figure 78. Programming the Flash Waveforms (Continued)
DATA |
DATA HIGH |
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL 
BS2
1.A: Load Command “0001 0001”.
2.H: Load Address High Byte ($00 - $01)
3.B: Load Address Low Byte ($00 - $FF)
4.E: Load Data Low Byte ($00 - $FF)
L: Write Data Low Byte
1.Set BS to “0”. This selects low data.
2.Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.
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1228B–09/01
3.Wait until to RDY/BSY goes high before programming the next byte. (See Figure 79 for signal waveforms.)
The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered:
•The command needs to be loaded only once when writing or reading multiple memory locations.
•Address high byte only needs to be loaded before programming a new 256-word page in the EEPROM.
•Skip writing the data value $FF, that is, the contents of the entire EEPROM after a Chip Erase.
These considerations also apply to Flash, EEPROM and Signature bytes reading.
Figure 79. Programming the EEPROM Waveforms
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DATA |
$11 |
ADDR. HIGH ADDR. LOW |
DATA LOW |
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XA1 |
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XA2 |
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BS1 |
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XTAL1 |
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WR |
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RDY/BSY |
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+12V |
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RESET |
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OE |
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BS2 |
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Reading the Flash |
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PAGEL |
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The algorithm for reading the Flash memory is as follows (refer to “Programming the |
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Flash” on page 117 for details on command and address loading): |
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1.A: Load Command “0000 0010”.
2.H: Load Address High Byte ($00 - $1F)
3.B: Load Address Low Byte ($00 - $FF)
4.Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5.Set BS to “1”. The Flash word high byte can now be read at DATA.
6.Set OE to “1”.
Reading the EEPROM |
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the |
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Flash” on page 117 for details on command and address loading): |
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A: Load Command “0000 0011”. |
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2. |
H: Load Address High Byte ($00 - $01) |
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3. |
B: Load Address ($00 - $FF) |
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4. |
Set |
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to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at |
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DATA. |
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5. |
Set |
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to “1”. |
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OE |
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120 ATmega161(L)
1228B–09/01