Материал: DOC1228
ATmega161(L)
Figure 98. I/O Pin Input Threshold vs. VCC
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I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC |
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2.5 |
TA = 25˚C |
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(V) |
2 |
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VOLTAGE |
1.5 |
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THRESHOLD |
1 |
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0.5 |
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0 |
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2.7 |
4.0 |
5.0 |
VCC
Figure 99. I/O Pin Input Hysteresis vs. VCC
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I/O PIN INPUT HYSTERESIS vs. VCC |
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0.18 |
TA = 25˚C |
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0.16 |
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0.14 |
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(V) |
0.12 |
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HYSTERESIS |
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0.1 |
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0.08 |
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0.06 |
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IINPUT |
0.04 |
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0.02 |
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0 |
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2.7 |
4.0 |
5.0 |
VCC
141
1228B–09/01
Register Summary(1)(2)
Address |
Name |
Bit 7 |
Bit 6 |
Bit 5 |
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Bit 4 |
Bit 3 |
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Bit 2 |
Bit 1 |
Bit 0 |
Page |
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$3F |
($5F) |
SREG |
I |
T |
H |
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S |
V |
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N |
Z |
C |
page 21 |
$3E |
($5E) |
SPH |
SP15 |
SP14 |
SP13 |
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SP12 |
SP11 |
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SP10 |
SP9 |
SP8 |
page 22 |
$3D |
($5D) |
SPL |
SP7 |
SP6 |
SP5 |
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SP4 |
SP3 |
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SP2 |
SP1 |
SP0 |
page 22 |
$3C |
($5C) |
Reserved |
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$3B |
($5B) |
GIMSK |
INT1 |
INT0 |
INT2 |
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- |
- |
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- |
- |
- |
page 31 |
$3A |
($5A) |
GIFR |
INTF1 |
INTF0 |
INTF2 |
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page 31 |
$39 |
($59) |
TIMSK |
TOIE1 |
OCIE1A |
OCIE1B |
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TOIE2 |
TICIE1 |
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OCIE2 |
TOIE0 |
OCIE0 |
page 32 |
$38 |
($58) |
TIFR |
TOV1 |
OCF1A |
OCF1B |
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TOV2 |
ICF1 |
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OCFI2 |
TOV0 |
OCIF0 |
page 33 |
$37 |
($57) |
SPMCR |
- |
- |
- |
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- |
LBSET |
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PGWRT |
PGERS |
SPMEN |
page 112 |
$36 |
($56) |
EMCUCR |
SM0 |
SRL2 |
SRL1 |
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SRL0 |
SRW01 |
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SRW00 |
SRW11 |
ISC2 |
page 36 |
$35 |
($55) |
MCUCR |
SRE |
SRW10 |
SE |
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SM1 |
ISC11 |
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ISC10 |
ISC01 |
ISC00 |
page 34 |
$34 |
($54) |
MCUSR |
- |
- |
- |
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- |
WDRF |
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BORF |
EXTRF |
PORF |
page 29 |
$33 |
($53) |
TCCR0 |
FOC0 |
PWM0 |
COM01 |
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COM00 |
CTC0 |
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CS02 |
CS01 |
CS00 |
page 42 |
$32 |
($52) |
TCNT0 |
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Timer/Counter0 Counter Register |
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page 44 |
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$31 |
($51) |
OCR0 |
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Timer/Counter0 Output Compare Register |
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page 44 |
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$30 |
($50) |
SFIOR |
- |
- |
- |
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- |
- |
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- |
PSR2 |
PSR10 |
page 39 |
$2F |
($4F) |
TCCR1A |
COM1A1 |
COM1A0 |
COM1B1 |
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COM1B0 |
FOC1A |
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FOC1B |
PWM11 |
PWM10 |
page 50 |
$2E |
($4E) |
TCCR1B |
ICNC1 |
ICES1 |
- |
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- |
CTC1 |
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CS12 |
CS11 |
CS10 |
page 52 |
$2D |
($4D) |
TCNT1H |
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Timer/Counter1 - Counter Register High Byte |
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page 53 |
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$2C |
($4C) |
TCNT1L |
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Timer/Counter1 - Counter Register Low Byte |
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page 53 |
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$2B |
($4B) |
OCR1AH |
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Timer/Counter1 - Output Compare Register A High Byte |
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page 53 |
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$2A |
($4A) |
OCR1AL |
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Timer/Counter1 - Output Compare Register A Low Byte |
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page 53 |
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$29 |
($49) |
OCR1BH |
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Timer/Counter1 - Output Compare Register B High Byte |
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page 54 |
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$28 |
($48) |
OCR1BL |
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Timer/Counter1 - Output Compare Register B Low Byte |
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page 54 |
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$27 |
($47) |
TCCR2 |
FOC2 |
PWM2 |
COM21 |
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COM20 |
CTC2 |
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CS22 |
CS21 |
CS20 |
page 42 |
$26 |
($46) |
ASSR |
- |
- |
- |
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- |
AS20 |
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TCON2UB |
OCR2UB |
TCR2UB |
page 46 |
$25 |
($45) |
ICR1H |
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Timer/Counter1 - Input Capture Register High Byte |
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page 54 |
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$24 |
($44) |
ICR1L |
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Timer/Counter1 - Input Capture Register Low Byte |
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page 54 |
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$23 |
($43) |
TCNT2 |
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Timer/Counter2 Counter Register |
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page 44 |
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$22 |
($42) |
OCR2 |
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Timer/Counter2 Output Compare Register |
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page 44 |
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$21 |
($41) |
WDTCR |
- |
- |
- |
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WDTOE |
WDE |
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WDP2 |
WDP1 |
WDP0 |
page 58 |
$20 |
($40) |
UBRRHI |
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UBRR1[11:8] |
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UBRR0[11:8] |
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page 76 |
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$1F |
($3F) |
EEARH |
- |
- |
- |
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- |
- |
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- |
- |
EEAR8 |
page 60 |
$1E |
($3E) |
EEARL |
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EEPROM Address Register Low Byte |
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page 60 |
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$1D |
($3D) |
EEDR |
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EEPROM Data Register |
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page 60 |
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$1C |
($3C) |
EECR |
- |
- |
- |
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- |
EERIE |
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EEMWE |
EEWE |
EERE |
page 61 |
$1B |
($3B) |
PORTA |
PORTA7 |
PORTA6 |
PORTA5 |
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PORTA4 |
PORTA3 |
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PORTA2 |
PORTA1 |
PORTA0 |
page 87 |
$1A |
($3A) |
DDRA |
DDA7 |
DDA6 |
DDA5 |
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DDA4 |
DDA3 |
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DDA2 |
DDA1 |
DDA0 |
page 87 |
$19 |
($39) |
PINA |
PINA7 |
PINA6 |
PINA5 |
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PINA4 |
PINA3 |
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PINA2 |
PINA1 |
PINA0 |
page 87 |
$18 |
($38) |
PORTB |
PORTB7 |
PORTB6 |
PORTB5 |
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PORTB4 |
PORTB3 |
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PORTB2 |
PORTB1 |
PORTB0 |
page 89 |
$17 |
($37) |
DDRB |
DDB7 |
DDB6 |
DDB5 |
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DDB4 |
DDB3 |
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DDB2 |
DDB1 |
DDB0 |
page 89 |
$16 |
($36) |
PINB |
PINB7 |
PINB6 |
PINB5 |
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PINB4 |
PINB3 |
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PINB2 |
PINB1 |
PINB0 |
page 89 |
$15 |
($35) |
PORTC |
PORTC7 |
PORTC6 |
PORTC5 |
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PORTC4 |
PORTC3 |
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PORTC2 |
PORTC1 |
PORTC0 |
page 96 |
$14 |
($34) |
DDRC |
DDC7 |
DDC6 |
DDC5 |
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DDC4 |
DDC3 |
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DDC2 |
DDC1 |
DDC0 |
page 96 |
$13 |
($33) |
PINC |
PINC7 |
PINC6 |
PINC5 |
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PINC4 |
PINC3 |
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PINC2 |
PINC1 |
PINC0 |
page 96 |
$12 |
($32) |
PORTD |
PORTD7 |
PORTD6 |
PORTD5 |
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PORTD4 |
PORTD3 |
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PORTD2 |
PORTD1 |
PORTD0 |
page 98 |
$11 |
($31) |
DDRD |
DDD7 |
DDD6 |
DDD5 |
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DDD4 |
DDD3 |
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DDD2 |
DDD1 |
DDD0 |
page 98 |
$10 |
($30) |
PIND |
PIND7 |
PIND6 |
PIND5 |
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PIND4 |
PIND3 |
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PIND2 |
PIND1 |
PIND0 |
page 98 |
$0F |
($2F) |
SPDR |
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SPI Data Register |
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page 67 |
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$0E |
($2E) |
SPSR |
SPIF |
WCOL |
- |
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- |
- |
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- |
- |
SPI2X |
page 67 |
$0D |
($2D) |
SPCR |
SPIE |
SPE |
DORD |
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MSTR |
CPOL |
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CPHA |
SPR1 |
SPR0 |
page 66 |
$0C |
($2C) |
UDR0 |
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UART0 I/O Data Register |
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page 72 |
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$0B |
($2B) |
UCSR0A |
RXC0 |
TXC0 |
UDRE0 |
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FE0 |
OR0 |
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- |
U2X0 |
MPCM0 |
page 72 |
$0A |
($2A) |
UCSR0B |
RXCIE0 |
TXCIE0 |
UDRIE0 |
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RXEN0 |
TXEN0 |
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CHR90 |
RXB80 |
TXB80 |
page 74 |
$09 |
($29) |
UBRR0 |
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UART0 Baud Rate Register |
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page 76 |
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$08 |
($28) |
ACSR |
ACD |
AINBG |
ACO |
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ACI |
ACIE |
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ACIC |
ACIS1 |
ACIS0 |
page 79 |
$07 |
($27) |
PORTE |
- |
- |
- |
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- |
- |
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PORTE2 |
PORTE1 |
PORTE0 |
page 104 |
$06 |
($26) |
DDRE |
- |
- |
- |
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- |
- |
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DDE2 |
DDE1 |
DDE0 |
page 104 |
$05 |
($25) |
PINE |
- |
- |
- |
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- |
- |
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PINE2 |
PINE1 |
PINE0 |
page 104 |
$04 |
($24) |
Reserved |
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$03 |
($23) |
UDR1 |
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UART1 I/O Data Register |
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page 72 |
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$02 |
($22) |
UCSR1A |
RXC1 |
TXC1 |
UDRE1 |
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FE1 |
OR1 |
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- |
U2X1 |
MPCM1 |
page 74 |
$01 |
($21) |
UCSR1B |
RXCIE1 |
TXCIE1 |
UDRIE1 |
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RXEN1 |
TXEN1 |
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CHR91 |
RXB81 |
TXB81 |
page 72 |
$00 |
($20) |
UBRR1 |
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UART1 Baud Rate Register |
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page 76 |
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142 ATmega161(L)
1228B–09/01
ATmega161(L)
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
2.Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
143
1228B–09/01
Instruction Set Summary
Mnemonic |
Operands |
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Description |
Operation |
Flags |
# Clocks |
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ARITHMETIC AND LOGIC INSTRUCTIONS |
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ADD |
Rd, Rr |
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Add Two Registers |
Rd ← Rd + Rr |
Z,C,N,V,H |
1 |
ADC |
Rd, Rr |
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Add with Carry Two Registers |
Rd ← Rd + Rr + C |
Z,C,N,V,H |
1 |
ADIW |
Rdl, K |
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Add Immediate to Word |
Rdh:Rdl ← Rdh:Rdl + K |
Z,C,N,V,S |
2 |
SUB |
Rd, Rr |
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Subtract Two Registers |
Rd ← Rd - Rr |
Z,C,N,V,H |
1 |
SUBI |
Rd, K |
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Subtract Constant from Register |
Rd ← Rd - K |
Z,C,N,V,H |
1 |
SBC |
Rd, Rr |
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Subtract with Carry Two Registers |
Rd ← Rd - Rr - C |
Z,C,N,V,H |
1 |
SBCI |
Rd, K |
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Subtract with Carry Constant from Reg. |
Rd ← Rd - K - C |
Z,C,N,V,H |
1 |
SBIW |
Rdl, K |
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Subtract Immediate from Word |
Rdh:Rdl ← Rdh:Rdl - K |
Z,C,N,V,S |
2 |
AND |
Rd, Rr |
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Logical AND Registers |
Rd ← Rd • Rr |
Z,N,V |
1 |
ANDI |
Rd, K |
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Logical AND Register and Constant |
Rd ← Rd • K |
Z,N,V |
1 |
OR |
Rd, Rr |
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Logical OR Registers |
Rd ← Rd v Rr |
Z,N,V |
1 |
ORI |
Rd, K |
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Logical OR Register and Constant |
Rd ← Rd v K |
Z,N,V |
1 |
EOR |
Rd, Rr |
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Exclusive OR Registers |
Rd ← Rd Rr |
Z,N,V |
1 |
COM |
Rd |
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One’s Complement |
Rd ← $FF - Rd |
Z,C,N,V |
1 |
NEG |
Rd |
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Two’s Complement |
Rd ← $00 - Rd |
Z,C,N,V,H |
1 |
SBR |
Rd, K |
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Set Bit(s) in Register |
Rd ← Rd v K |
Z,N,V |
1 |
CBR |
Rd, K |
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Clear Bit(s) in Register |
Rd ← Rd • ($FF - K) |
Z,N,V |
1 |
INC |
Rd |
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Increment |
Rd ← Rd + 1 |
Z,N,V |
1 |
DEC |
Rd |
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Decrement |
Rd ← Rd - 1 |
Z,N,V |
1 |
TST |
Rd |
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Test for Zero or Minus |
Rd ← Rd • Rd |
Z,N,V |
1 |
CLR |
Rd |
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Clear Register |
Rd ← Rd Rd |
Z,N,V |
1 |
SER |
Rd |
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Set Register |
Rd ← $FF |
None |
1 |
MUL |
Rd, Rr |
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Multiply Unsigned |
R1:R0 ← Rd x Rr |
Z,C |
2 |
MULS |
Rd, Rr |
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Multiply Signed |
R1:R0 ← Rd x Rr |
Z,C |
2 |
MULSU |
Rd, Rr |
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Multiply Signed with Unsigned |
R1:R0 ← Rd x Rr |
Z,C |
2 |
FMUL |
Rd, Rr |
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Fractional Multiply Unsigned |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
FMULS |
Rd, Rr |
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Fractional Multiply Signed |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
FMULSU |
Rd, Rr |
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Fractional Multiply Signed with Unsigned |
R1:R0 ← (Rd x Rr) << 1 |
Z,C |
2 |
BRANCH INSTRUCTIONS |
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RJMP |
k |
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Relative Jump |
PC ← PC + k + 1 |
None |
2 |
IJMP |
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Indirect Jump to (Z) |
PC ← Z |
None |
2 |
JMP |
k |
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Direct Jump |
PC ← k |
None |
3 |
RCALL |
k |
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Relative Subroutine Call |
PC ← PC + k + 1 |
None |
3 |
ICALL |
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Indirect Call to (Z) |
PC ← Z |
None |
3 |
CALL |
k |
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Direct Subroutine Call |
PC ← k |
None |
4 |
RET |
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Subroutine Return |
PC ← STACK |
None |
4 |
RETI |
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Interrupt Return |
PC ← STACK |
I |
4 |
CPSE |
Rd, Rr |
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Compare, Skip if Equal |
if (Rd = Rr) PC ← PC + 2 or 3 |
None |
1/2/3 |
CP |
Rd, Rr |
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Compare |
Rd - Rr |
Z,N,V,C,H |
1 |
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CPC |
Rd, Rr |
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Compare with Carry |
Rd - Rr - C |
Z,N,V,C,H |
1 |
CPI |
Rd, K |
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Compare Register with Immediate |
Rd - K |
Z,N,V,C,H |
1 |
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SBRC |
Rr, b |
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Skip if Bit in Register Cleared |
if (Rr(b) = 0) PC ← PC + 2 or 3 |
None |
1/2/3 |
SBRS |
Rr, b |
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Skip if Bit in Register is Set |
if (Rr(b) = 1) PC ← PC + 2 or 3 |
None |
1/2/3 |
SBIC |
P, b |
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Skip if Bit in I/O Register Cleared |
if (P(b) = 0) PC ← PC + 2 or 3 |
None |
1/2/3 |
SBIS |
P, b |
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Skip if Bit in I/O Register is Set |
if (P(b) = 1) PC ← PC + 2 or 3 |
None |
1/2/3 |
BRBS |
s, k |
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Branch if Status Flag Set |
if (SREG(s) = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRBC |
s, k |
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Branch if Status Flag Cleared |
if (SREG(s) = 0) then PC ← PC + k + 1 |
None |
1/2 |
BREQ |
k |
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Branch if Equal |
if (Z = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRNE |
k |
|
Branch if Not Equal |
if (Z = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRCS |
k |
|
Branch if Carry Set |
if (C = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRCC |
k |
|
Branch if Carry Cleared |
if (C = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRSH |
k |
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Branch if Same or Higher |
if (C = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRLO |
k |
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Branch if Lower |
if (C = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRMI |
k |
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Branch if Minus |
if (N = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRPL |
k |
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Branch if Plus |
if (N = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRGE |
k |
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Branch if Greater or Equal, Signed |
if (N V = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRLT |
k |
|
Branch if Less than Zero, Signed |
if (N V = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRHS |
k |
|
Branch if Half-carry Flag Set |
if (H = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRHC |
k |
|
Branch if Half-carry Flag Cleared |
if (H = 0) then PC ← PC + k + 1 |
None |
1/2 |
144 ATmega161(L)
1228B–09/01
ATmega161(L)
Instruction Set Summary (Continued)
Mnemonic |
Operands |
Description |
Operation |
Flags |
# Clocks |
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BRTS |
k |
Branch if T-flag Set |
if (T = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRTC |
k |
Branch if T-flag Cleared |
if (T = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRVS |
k |
Branch if Overflow Flag is Set |
if (V = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRVC |
k |
Branch if Overflow Flag is Cleared |
if (V = 0) then PC ← PC + k + 1 |
None |
1/2 |
BRIE |
k |
Branch if Interrupt Enabled |
if (I = 1) then PC ← PC + k + 1 |
None |
1/2 |
BRID |
k |
Branch if Interrupt Disabled |
if (I = 0) then PC ← PC + k + 1 |
None |
1/2 |
DATA TRANSFER INSTRUCTIONS |
|
|
|
|
|
MOV |
Rd, Rr |
Move between Registers |
Rd ← Rr |
None |
1 |
MOVW |
Rd, Rr |
Copy Register Word |
Rd+1:Rd ← Rr+1:Rr |
None |
1 |
LDI |
Rd, K |
Load Immediate |
Rd ← K |
None |
1 |
LD |
Rd, X |
Load Indirect |
Rd ← (X) |
None |
2 |
LD |
Rd, X+ |
Load Indirect and Post-inc. |
Rd ← (X), X ← X + 1 |
None |
2 |
LD |
Rd, -X |
Load Indirect and Pre-dec. |
X ← X - 1, Rd ← (X) |
None |
2 |
LD |
Rd, Y |
Load Indirect |
Rd ← (Y) |
None |
2 |
LD |
Rd, Y+ |
Load Indirect and Post-inc. |
Rd ← (Y), Y ← Y + 1 |
None |
2 |
LD |
Rd, -Y |
Load Indirect and Pre-dec. |
Y ← Y - 1, Rd ← (Y) |
None |
2 |
LDD |
Rd, Y+q |
Load Indirect with Displacement |
Rd ← (Y + q) |
None |
2 |
LD |
Rd, Z |
Load Indirect |
Rd ← (Z) |
None |
2 |
LD |
Rd, Z+ |
Load Indirect and Post-inc. |
Rd ← (Z), Z ← Z + 1 |
None |
2 |
LD |
Rd, -Z |
Load Indirect and Pre-dec. |
Z ← Z - 1, Rd ← (Z) |
None |
2 |
LDD |
Rd, Z+q |
Load Indirect with Displacement |
Rd ← (Z + q) |
None |
2 |
LDS |
Rd, k |
Load Direct from SRAM |
Rd ← (k) |
None |
2 |
ST |
X, Rr |
Store Indirect |
(X) ← Rr |
None |
2 |
ST |
X+, Rr |
Store Indirect and Post-inc. |
(X) ← Rr, X ← X + 1 |
None |
2 |
ST |
-X, Rr |
Store Indirect and Pre-dec. |
X ← X - 1, (X) ← Rr |
None |
2 |
ST |
Y, Rr |
Store Indirect |
(Y) ← Rr |
None |
2 |
ST |
Y+, Rr |
Store Indirect and Post-inc. |
(Y) ← Rr, Y ← Y + 1 |
None |
2 |
ST |
-Y, Rr |
Store Indirect and Pre-dec. |
Y ← Y - 1, (Y) ← Rr |
None |
2 |
STD |
Y+q, Rr |
Store Indirect with Displacement |
(Y + q) ← Rr |
None |
2 |
ST |
Z, Rr |
Store Indirect |
(Z) ← Rr |
None |
2 |
ST |
Z+, Rr |
Store Indirect and Post-inc. |
(Z) ← Rr, Z ← Z + 1 |
None |
2 |
ST |
-Z, Rr |
Store Indirect and Pre-dec. |
Z ← Z - 1, (Z) ← Rr |
None |
2 |
STD |
Z+q, Rr |
Store Indirect with Displacement |
(Z + q) ← Rr |
None |
2 |
STS |
k, Rr |
Store Direct to SRAM |
(k) ← Rr |
None |
2 |
LPM |
|
Load Program Memory |
R0 ← (Z) |
None |
3 |
LPM |
Rd, Z |
Load Program Memory |
Rd ← (Z) |
None |
3 |
LPM |
Rd, Z+ |
Load Program Memory and Post-inc. |
Rd ← (Z), Z ← Z + 1 |
None |
3 |
SPM |
|
Store Program Memory |
(Z) ← R1:R0 |
None |
- |
IN |
Rd, P |
In Port |
Rd ← P |
None |
1 |
OUT |
P, Rr |
Out Port |
P ← Rr |
None |
1 |
PUSH |
Rr |
Push Register on Stack |
STACK ← Rr |
None |
2 |
POP |
Rd |
Pop Register from Stack |
Rd ← STACK |
None |
2 |
BIT AND BIT-TEST INSTRUCTIONS |
|
|
|
|
|
SBI |
P, b |
Set Bit in I/O Register |
I/O(P,b) ← 1 |
None |
2 |
CBI |
P, b |
Clear Bit in I/O Register |
I/O(P,b) ← 0 |
None |
2 |
LSL |
Rd |
Logical Shift Left |
Rd(n+1) ← Rd(n), Rd(0) ← 0 |
Z,C,N,V |
1 |
LSR |
Rd |
Logical Shift Right |
Rd(n) ← Rd(n+1), Rd(7) ← 0 |
Z,C,N,V |
1 |
ROL |
Rd |
Rotate Left through Carry |
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) |
Z,C,N,V |
1 |
ROR |
Rd |
Rotate Right through Carry |
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) |
Z,C,N,V |
1 |
ASR |
Rd |
Arithmetic Shift Right |
Rd(n) ← Rd(n+1), n = 0..6 |
Z,C,N,V |
1 |
SWAP |
Rd |
Swap Nibbles |
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) |
None |
1 |
BSET |
s |
Flag Set |
SREG(s) ← 1 |
SREG(s) |
1 |
BCLR |
s |
Flag Clear |
SREG(s) ← 0 |
SREG(s) |
1 |
BST |
Rr, b |
Bit Store from Register to T |
T ← Rr(b) |
T |
1 |
BLD |
Rd, b |
Bit Load from T to Register |
Rd(b) ← T |
None |
1 |
SEC |
|
Set Carry |
C ← 1 |
C |
1 |
CLC |
|
Clear Carry |
C ← 0 |
C |
1 |
SEN |
|
Set Negative Flag |
N ← 1 |
N |
1 |
CLN |
|
Clear Negative Flag |
N ← 0 |
N |
1 |
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1228B–09/01