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ATmega161(L)

External Data Memory Timing

Table 51. External Data Memory Characteristics, 4.0 - 5.5 Volts, No Wait State

				8 MHz Oscillator		Variable Oscillator

	Symbol		Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL		Oscillator Frequency			0.0	8.0	MHz
1	tLHLL		ALE Pulse Width	95		1.0tCLCL-30		ns
2	tAVLL		Address Valid A to ALE Low	22.5		0.5tCLCL-40(1)		ns
3a	tLLAX_ST		Address Hold After ALE Low,	10		10		ns
3a	tLLAX_ST		write access	10		10		ns
			write access

3b	tLLAX_LD		Address Hold after ALE Low,	15		15		ns
3b	tLLAX_LD		read access	15		15		ns
			read access

4	tAVLLC		Address Valid C to ALE Low	22.5		0.5tCLCL-40(1)		ns
5	tAVRL		Address Valid to RD Low	95		1.0tCLCL-30		ns
6	tAVWL		Address Valid to WR Low	95		1.0tCLCL-30		ns
7	tLLWL		ALE Low to WR Low	42.5	145	0.5tCLCL-20(2)	0.5tCLCL+20(2)	ns
8	tLLRL		ALE Low to RD Low	42.5	145	0.5tCLCL-20(2)	0.5tCLCL+20(2)	ns
9	tDVRH		Data Setup to RD High	60		60		ns
10	tRLDV		Read Low to Data Valid		65		65	ns
11	tRHDX		Data Hold After RD High	0		0		ns
12	tRLRH		RD Pulse Width	105		1.0tCLCL-20		ns
13	t	DVWL	Data Setup to WR Low	27.5		0.5t -35(1)		ns
		DVWL				CLCL
14	tWHDX		Data Hold After WR High	27.5		0.5tCLCL-35(1)		ns
15	tDVWH		Data Valid to WR High	95		1.0tCLCL-30		ns
16	tWLWH		WR Pulse Width	105		1.0tCLCL-20		ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 52. External Data Memory Characteristics, 4.0 - 5.5 Volts, 1 Cycle Wait State

			8 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8.0	MHz
10	tRLDV	Read Low to Data Valid		185		2.0tCLCL-65	ns
12	tRLRH	RD Pulse Width	230		2.0tCLCL-20		ns
15	tDVWH	Data Valid to WR High	220		2.0tCLCL-30		ns
16	tWLWH	WR Pulse Width	230		2.0tCLCL-20		ns

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Table 53. External Data Memory Characteristics, 4.0 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			8 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8.0	MHz
10	tRLDV	Read Low to Data Valid		310		3.0tCLCL-65	ns
12	tRLRH	RD Pulse Width	355		3.0tCLCL-20		ns
15	tDVWH	Data Valid to WR High	345		3.0tCLCL-30		ns
16	tWLWH	WR Pulse Width	35		3.0tCLCL-20		ns

Table 54. External Data Memory Characteristics, 4.0 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			8 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8.0	MHz
10	tRLDV	Read Low to Data Valid		310		3.0tCLCL-65	ns
12	tRLRH	RD Pulse Width	355		3.0tCLCL-20		ns
14	tWHDX	Data Hold After WR High	152.5		1.5tCLCL-35		ns
15	tDVWH	Data Valid to WR High	345		3.0tCLCL-30		ns
16	tWLWH	WR Pulse Width	355		3.0tCLCL-20		ns

Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	4.0	MHz
1	tLHLL	ALE Pulse Width	195		tCLCL-55		ns
2	tAVLL	Address Valid A to ALE Low	60		0.5tCLCL-65		ns
3a	tLLAX_ST	Address Hold After ALE Low,	10		10		ns
3a	tLLAX_ST	write access	10		10		ns
		write access

3b	tLLAX_LD	Address Hold after ALE Low,	15		15		ns
3b	tLLAX_LD	read access	15		15		ns
		read access

4	tAVLLC	Address Valid C to ALE Low	60		0.5tCLCL-65		ns
5	tAVRL	Address Valid to RD Low	200		1.0tCLCL-50		ns
6	tAVWL	Address Valid to WR Low	200		1.0tCLCL-50		ns
7	tLLWL	ALE Low to WR Low	105	145	0.5tCLCL-20	0.5tCLCL+20	ns
8	tLLRL	ALE Low to RD Low	105	145	0.5tCLCL-20	0.5tCLCL+20	ns
9	tDVRH	Data Setup to RD High	95		95		ns
10	tRLDV	Read Low to Data Valid		165		165	ns
11	tRHDX	Data Hold After RD High	0		0		ns

132 ATmega161(L)

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ATmega161(L)

Table 55. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait State					(Continued)
			4 MHz Oscillator			Variable Oscillator

	Symbol	Parameter	Min	Max		Min	Max	Unit

12	tRLRH	RD Pulse Width	230			1.0tCLCL-20		ns
13	tDVWL	Data Setup to WR Low	70			0.5tCLCL-55		ns
14	tWHDX	Data Hold After WR High	125			0.5tCLCL-0		ns
15	tDVWH	Data Valid to WR High	210			1.0tCLCL-40		ns
16	tWLWH	WR Pulse Width	230			1.0tCLCL-20		ns

Table 56. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	4.0	MHz
10	tRLDV	Read Low to Data Valid		335		2.0tCLCL-165	ns
12	tRLRH	RD Pulse Width	480		2.0tCLCL-20		ns
15	tDVWH	Data Valid to WR High	460		2.0tCLCL-40		ns
16	tWLWH	WR Pulse Width	480		2.0tCLCL-20		ns

Table 57. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	4.0	MHz
10	tRLDV	Read Low to Data Valid		585		3.0tCLCL-165	ns
12	tRLRH	RD Pulse Width	730		3.0tCLCL-20		ns
15	tDVWH	Data Valid to WR High	710		3.0tCLCL-40		ns
16	tWLWH	WR Pulse Width	730		3.0tCLCL-20		ns

Table 58. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	4.0	MHz
10	tRLDV	Read Low to Data Valid		585		3.0tCLCL-165	ns
12	tRLRH	RD Pulse Width	730		3.0tCLCL-20		ns
14	tWHDX	Data Hold After WR High	375		1.5tCLCL-0		ns
15	tDVWH	Data Valid to WR High	710		3.0tCLCL-40		ns
16	tWLWH	WR Pulse Width	730		3.0tCLCL-20		ns

133

1228B–09/01

Figure 84. External Memory Timing (SRWn1 = 0, SRWn0 = 0)
	T1			T2	T3		T4
System Clock Ø
			1
ALE
			4	7
Address [15..8]	Prev. addr.	XX			Address		XX
					15
			2	3a	13
Data/Address [7..0]	Prev. data	XX	Address		Data	14	XX
						14	Write
				6	16		Write
				6	16
WR
				3b	9	11
Data/Address [7..0]	Prev. data	XX	Address		Data		XX
				5	10		Read
				8	12		Read
				8	12
RD
Figure 85. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

System Clock Ø

ALE

Address [15..8]

Data/Address [7..0]

T1			T2	T3	T4		T5
		1
		4	7
Prev. addr.	XX			Address			XX
					15
		2	3a	13
Prev. data	XX	Address		Data		14	XX
						14	Write
			6		16		Write
			6		16
			3b		9	11
Prev. data	XX	Address		Data			XX
			5	10			Read
			8		12		Read
			8		12

134 ATmega161(L)

1228B–09/01

							ATmega161(L)
Figure 86. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
	T1			T2	T3	T4	T5		T6
System Clock Ø
			1
ALE
			4	7
Address [15..8]	Prev. addr.	XX			Address				XX
						15
			2	3a	13
Data/Address [7..0]	Prev. data	XX	Address		Data			14	XX
								14	Write
				6		16			Write
				6		16
WR
				3b		9		11
Data/Address [7..0]	Prev. data	XX	Address		Data				XX
				5	10				Read
				8		12			Read
RD

Figure 87. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

	T1			T2	T3	T4	T5	T6		T7
System Clock Ø
			1
ALE
			4	7
Address [15..8]	Prev. addr.	XX			Address	15				XX
						15
			2	3a	13
Data/Address [7..0]	Prev. data	XX	Address		Data				14	XX
									14	Write
				6		16				Write
WR
				3b		9		11
Data/Address [7..0]	Prev. data	XX	Address		Data					XX
				5	10					Read
				8		12				Read
RD

Note: 1. The ALE pulse in the last period (T4 - T7) is only present if the next instruction accesses the RAM (internal or external). The data and address will only change in T4 - T7 if ALE is present (the next instruction accesses the RAM).

135

1228B–09/01

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