Материал: DOC1228

Parallel Programming

Characteristics

Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA. 3. Set OE to “1”.

Figure 80. Parallel Programming Timing

tXLWL

tDVXH tXLDX

Data & Control (DATA, XA0/1, BS1)

Serial Downloading

Notes: 1. tWLRH is valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits commands.

2.tWLRH_CE is valid for the Chip Erase command.

3.tWLRH_FLASH is valid for the Write Flash command.

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first, before program/erase operations can be executed.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The chip erase operation turns the contents of every memory location in both the program and EEPROM arrays into $FF.

The program and EEPROM memory arrays have separate address spaces:

$0000 to $1FFF for program memory and $0000 to $01FF for EEPROM memory.

Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycles

High: > 2 XTAL1 clock cycles

Serial Programming

Algorithm

Data Polling Flash

When writing serial data to the ATmega161, data is clocked on the rising edge of SCK.

When reading data from the ATmega161, data is clocked on the falling edge of SCK. See Figure 81, Figure 82 and Table 49 for timing details.

To program and verify the ATmega161 in the serial programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 48):

1.Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles’ duration after SCK has been set to “0”.

2.Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB5.

3.The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether or not the echo is correct, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.

4.If a chip erase is performed (must be done to erase the Flash), give RESET a positive pulse and start over from step 2.

5.The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the

address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page (please refer to Table 46). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming.

6.The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not

used, the user must wait at least tWD_EEPROM before issuing the next byte (please refer to Table 46). In a chip-erased device, no $FFs in the data file(s) need to be programmed.

7.Any memory location can be verified by using the Read instruction, which returns the content at the selected address at serial output MISO/PB6.

8.At the end of the programming session, RESET can be set high to commence normal operation.

9.Power-off sequence (if needed):

Set XTAL1 to “0” (if a crystal is not used). Set RESET to “1”.

Turn VCC power off.

When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the FLASH will not work for the value $FF, so when programming this value, the user will have to wait for at least