Материал: DOC1228
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Table 48. Serial Programming Instruction Set(1)
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Instruction Format |
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Instruction |
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Byte 1 |
Byte 2 |
Byte 3 |
Byte 4 |
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Operation |
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Programming Enable |
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1010 |
1100 |
0101 0011 |
xxxx xxxx |
xxxx xxxx |
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Enable Serial Programming after |
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RESET |
goes low. |
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Chip Erase |
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1010 |
1100 |
100x xxxx |
xxxx xxxx |
xxxx xxxx |
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Chip Erase EEPROM and Flash. |
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Read Program Memory |
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0010 |
H000 |
xxxa aaaa |
bbbb bbbb |
oooo oooo |
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Read H (high or low) data o from |
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program memory at word address |
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a:b. |
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Load Program Memory |
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0100 |
H000 |
xxxx xxxx |
xxbb bbbb |
iiii iiii |
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Write H (high or low) data i to |
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Page |
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program memory page at word |
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address b. |
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Write Program Memory |
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0100 |
1100 |
xxxa aaaa |
bbxx xxxx |
iiii iiii |
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Write program memory page at |
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Page |
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address a:b. |
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Read EEPROM Memory |
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1010 |
0000 |
xxxx xxxa |
bbbb bbbb |
oooo oooo |
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Read data o from EEPROM |
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memory at address a:b. |
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Write EEPROM Memory |
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1100 |
0000 |
xxxx xxxa |
bbbb bbbb |
iiii iiii |
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Write data i to EEPROM memory at |
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address a:b. |
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Read Lock Bits |
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0101 |
1000 |
xxxx xxxx |
xxxx xxxx |
xx65 4321 |
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Read Lock bits. “0” = programmed, |
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“1” = unprogrammed. |
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Write Lock Bits |
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1010 |
1100 |
111x xxxx |
xxxx xxxx |
1165 4321 |
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Write Lock bits. Set bits 6 - 1 = “0” |
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to program Lock bits. |
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Read Signature Byte |
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0011 |
0000 |
xxxx xxxx |
xxxx xxbb |
oooo oooo |
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Read Signature byte o at address |
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b. |
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Write Fuse Bits |
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1010 |
1100 |
101x xxxx |
xxxx xxxx |
1D1B A987 |
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Set bits D - A, 9 - 7 = “0” to |
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program, “1” to unprogram |
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Read Fuse Bits |
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0101 |
0000 |
xxxx xxxx |
xxxx xxxx |
xDCB A987 |
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Read Fuse bits. “0” = programmed, |
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“1” = unprogrammed |
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Note: 1. a = address high bits |
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b = address low bits |
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H = 0 – Low byte, 1 – High Byte |
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o = data out |
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i = data in |
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x = don’t care |
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1 = lock bit 1 |
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2 = lock bit 2 |
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3 = Boot Lock Bit1 |
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4 = Boot Lock Bit2 |
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5 = Boot Lock Bit11 |
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6 = Boot Lock Bit12 |
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7 = CKSEL0 Fuse |
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8 = CKSEL1 Fuse |
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9 = CKSEL2 Fuse |
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A = BODEN Fuse |
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B = BODLEVEL Fuse |
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C = SPIEN Fuse |
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D = BOOTRST Fuse |
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126 ATmega161(L)
1228B–09/01
ATmega161(L)
Serial Programming |
Figure 82. Serial Programming Timing |
Characteristics |
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MOSI
tOVSH |
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tSHOX |
tSLSH |
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SCK
tSHSL
MISO
tSLIV
Table 49. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 5.5V (unless otherwise noted)
Symbol |
Parameter |
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Min |
Typ |
Max |
Units |
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1/tCLCL |
Oscillator Frequency |
(VCC = 2.7 - 5.5V) |
0 |
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4 |
MHz |
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(VCC = 4.0 - 5.5V) |
0 |
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8 |
MHz |
tCLCL |
Oscillator Period |
(VCC = 2.7 - 5.5V) |
250 |
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ns |
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(VCC = 4.0 - 5.5V) |
125 |
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tSHSL |
SCK Pulse Width High |
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2 tCLCL |
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tSLSH |
SCK Pulse Width Low |
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2 tCLCL |
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tOVSH |
MOSI Setup to SCK High |
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tCLCL |
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tSHOX |
MOSI Hold after SCK High |
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2 tCLCL |
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tSLIV |
SCK Low to MISO Valid |
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10 |
16 |
32 |
ns |
127
1228B–09/01
Electrical Characteristics
Absolute Maximum Ratings*
..................................Operating Temperature |
-55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or |
Voltage on Any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with Respect to Ground ............................. |
-1.0V to VCC + 0.5V |
operational sections of this specification is not |
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Voltage on |
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with Respect to Ground -1.0V to +13.0V |
implied. Exposure to absolute maximum rating |
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RESET |
conditions for extended periods may affect |
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Maximum Operating Voltage |
6.6V |
device reliability. |
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DC Current per I/O Pin ............................................... |
40.0 mA |
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DC Current VCC and GND Pins ............................... |
200.0 mA |
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DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1)(2)(3)(4)(5)
Symbol |
Parameter |
Condition |
Min |
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Typ |
Max |
Units |
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VIL |
Input Low Voltage |
(Except XTAL1) |
-0.5 |
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0.3 VCC(1) |
V |
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VIL1 |
Input Low Voltage |
(XTAL1) |
-0.5 |
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0.2 VCC(1) |
V |
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VIH |
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(2) |
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Input High Voltage |
(Except XTAL1, RESET) |
0.6 VCC |
VCC + 0.5 |
V |
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VIH1 |
Input High Voltage |
(XTAL1) |
0.8 VCC |
(2) |
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VCC + 0.5 |
V |
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VIH2 |
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(2) |
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Input High Voltage |
(RESET) |
0.9 VCC |
VCC + 0.5 |
V |
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VOL |
Output Low Voltage(3) |
IOL = 20 mA, VCC = 5V |
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0.6 |
V |
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(Ports A,B,C,D) |
IOL = 10 mA, VCC = 3V |
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0.5 |
V |
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Output High Voltage(4) |
I |
OH |
= -3 mA, V = 5V |
4.2 |
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V |
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VOH |
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CC |
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(Ports A,B,C,D) |
IOH = -1.5 mA, VCC = 3V |
2.3 |
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V |
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IIL |
Input Leakage |
VCC = 5.5V, pin low |
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8.0 |
µA |
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Current I/O pin |
(absolute value) |
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IIH |
Input Leakage |
VCC = 5.5V, pin high |
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980 |
nA |
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Current I/O pin |
(absolute value) |
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RRST |
Reset Pull-up Resistor |
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100 |
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500 |
kΩ |
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RI/O |
I/O Pin Pull-up Resistor |
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35 |
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120 |
kΩ |
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Active mode, VCC = 3V, |
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3.0 |
mA |
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4 MHz |
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ICC |
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Idle mode VCC = 3V, |
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1.2 |
mA |
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Power Supply Current |
4 MHz |
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WDT enabled, VCC = 3V |
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9 |
15.0 |
µA |
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Power-down Mode(5) |
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WDT disabled, VCC = 3V |
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<1 |
2.0 |
µA |
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128 ATmega161(L)
1228B–09/01
ATmega161(L)
DC Characteristics (Continued)
T = -40°C to 85°C, V |
CC |
= 2.7V to 5.5V (unless otherwise noted)(1)(2)(3)(4)(5) |
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A |
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Symbol |
Parameter |
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Condition |
Min |
Typ |
Max |
Units |
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VACIO |
Analog Comparator |
VCC = 5V |
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40 |
mV |
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Input Offset Voltage |
Vin = VCC/2 |
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IACLK |
Analog Comparator |
VCC = 5V |
-50 |
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50 |
nA |
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Input Leakage Current |
Vin = VCC/2 |
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tACPD |
Analog Comparator |
VCC = 2.7V |
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750 |
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Propagation Delay |
VCC = 4.0V |
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500 |
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Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.
2.“Min” means the lowest value where the pin is guaranteed to be read as high.
3.Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 200 mA.
2] The sum of all IOL, for ports B0 - B7, D0 - D7 and XTAL2, should not exceed 100 mA.
3] The sum of all IOL, for ports A0 - A7, ALE, OC1B and C0 - C7 should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
4.Although each I/O port can source more than the test conditions (3 mA at VCC = 5V, 1.5 mA at VCC = 3V) under steady-state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 200 mA.
2] The sum of all IOH, for ports B0 - B7, D0 - D7 and XTAL2, should not exceed 100 mA.
3] The sum of all IOH, for ports A0 - A7, ALE, OC1B and C0 - C7 should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
5.Minimum VCC for power-down is 2V.
129
1228B–09/01
External Clock Drive
Waveforms
Figure 83. External Clock
VIH1
VIL1
Table 50. External Clock Drive(1)
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VCC = 2.7V to 5.5V |
VCC = 4.0V to 5.5V |
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Symbol |
Parameter |
Min |
Max |
Min |
Max |
Units |
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1/tCLCL |
Oscillator Frequency |
0 |
4 |
0 |
8 |
MHz |
tCLCL |
Clock Period |
250 |
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125 |
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ns |
tCHCX |
High Time |
100 |
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50 |
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ns |
tCLCX |
Low Time |
100 |
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50 |
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tCLCH |
Rise Time |
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1.6 |
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0.5 |
µs |
tCHCL |
Fall Time |
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1.6 |
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0.5 |
µs |
Notes: 1. See “External Data Memory Timing” for a description of how the duty cycle influences the timing for the external data memory.
130 ATmega161(L)
1228B–09/01