ATmega161(L)
• RXD1/AIN0 – Port B, Bit 2
AIN0, Analog Comparator Positive Input. This pin also serves as the positive input of the on-chip Analog Comparator.
RXD1, Receive Data (Data input pin for the UART1). When the UART1 receiver is enabled, this pin is configured as an input regardless of the value of DDRB2. When the UART1 forces this pin to be an input, a logical “1” in PORTB2 will turn on the internal pull-up.
• OC2/T1 – Port B, Bit 1
T1: Timer/Counter1 counter source. See “Timer/Counter1” on page 49 for further details.
OC2, Output compare match output: The PB1 pin can serve as an external output when the Timer/Counter2 compare matches. The PB1 pin has to be configured as an output (DDB1 set [one]) to serve this function. See “8-bit Timer/Counters T/C0 and T/C2” on page 40 for further details. The OC2 pin is also the output pin for the PWM mode timer function.
• OC0/T0 – Port B, Bit 0
T0: Timer/Counter0 counter source. See “8-bit Timer/Counters T/C0 and T/C2” on page 40 further details.
OC0, Output compare match output: The PB0 pin can serve as an external output when the Timer/Counter0 compare matches. The PB0 pin has to be configured as an output (DDB0 set [one]) to serve this function. See “8-bit Timer/Counters T/C0 and T/C2” on page 40 for further details and how to enable the output. The OC0 pin is also the output pin for the PWM mode timer function.
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Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures.
Figure 57. Port B Schematic Diagram (Pins PB0 and PB1)
DDBn
PBn
PORTBn
WP: |
WRITE PORTB |
COMx0 |
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WRITE DDRB |
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RL: |
READ PORTB LATCH |
COMP. MATCH x |
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READ PORTB PIN |
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RD: |
READ DDRB |
PWMx |
n:0,1
x: 0,2 |
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FOCx |
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CSn2 CSn1 CSn0
92 ATmega161(L)
1228B–09/01
ATmega161(L)
Figure 58. Port B Schematic Diagram (Pin PB2)
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MOS |
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PULL- |
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UP |
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RESET |
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D |
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DDB2 |
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C |
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WD |
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RESET |
PB2 |
Q |
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PORTB2 |
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C |
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RL |
WP |
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RP
RXEN1 |
RXD1 |
WP: |
WRITE PORTB |
WD: |
WRITE DDRB |
RL: |
READ PORTB LATCH |
RP: |
READ PORTB PIN |
RD: |
READ DDRB |
RXD1: |
UART1 RECEIVE DATA |
RXEN1: |
UART1 RECEIVE ENABLE |
AIN0: |
ANALOG COMPARATOR POSITIVE INPUT |
DATA BUS
AIN0
Figure 59. Port B Schematic Diagram (Pin PB3)
MOS
PULL-
UP
PB3
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RD |
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D |
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DDB3 |
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RL |
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WP |
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RP
TXEN1
TXD1
WP: |
WRITE PORTB |
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WRITE DDRB |
AIN1 |
RL: |
READ PORTB LATCH |
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RP: |
READ PORTB PIN |
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RD: |
READ DDRB |
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TXD1: |
UART1 TRANSMIT DATA |
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TXEN1: |
UART1 TRANSMIT ENABLE |
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AIN1: |
ANALOG COMPARATOR NEGATIVE INPUT |
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Figure 60. Port B Schematic Diagram (Pin PB4)
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RD |
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MOS |
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PULL- |
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UP |
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RESET |
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D |
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DDB4 |
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C |
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WD |
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RESET |
PB4 |
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PORTB4 |
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C |
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WP |
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RP
DATA BUS
WP: |
WRITE PORTB |
WD: |
WRITE DDRB |
RL: |
READ PORTB LATCH |
RP: |
READ PORTB PIN |
RD: |
READ DDRB |
MSTR: |
SPI MASTER ENABLE |
SPE: |
SPI ENABLE |
MSTR
SPE
SPI SS
Figure 61. Port B Schematic Diagram (Pin PB5)
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RD |
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MOS |
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PULL- |
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UP |
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RESET |
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Q |
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D |
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DDB5 |
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C |
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BUS |
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RESET |
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PB5 |
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D |
DATA |
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PORTB5 |
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C |
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RL |
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RP |
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WP: |
WRITE PORTB |
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MSTR |
WD: |
WRITE DDRB |
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RL: |
READ PORTB LATCH |
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SPI MASTER |
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READ PORTB PIN |
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RD: |
READ DDRB |
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OUT |
SPE: |
SPI ENABLE |
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MSTR MASTER SELECT |
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SPI SLAVE |
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IN |
94 ATmega161(L)
1228B–09/01
ATmega161(L)
Figure 62. Port B Schematic Diagram (Pin PB6)
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RD |
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MOS |
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PULL- |
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UP |
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RESET |
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Q |
R |
D |
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DDB6 |
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C |
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WD |
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BUS |
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RESET |
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PB6 |
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Q |
R |
D |
DATA |
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PORTB6 |
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C |
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RL |
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WP |
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RP |
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WP: WRITE PORTB
WD: WRITE DDRB
RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB
SPE: SPI ENABLE MSTR MASTER SELECT
MSTR
SPE
SPI SLAVE OUT
SPI MASTER IN
Figure 63. Port B Schematic Diagram (Pin PB7)
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RD |
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MOS |
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PULL- |
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UP |
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RESET |
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Q |
R |
D |
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DDB7 |
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C |
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WD |
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RESET |
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DATA |
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Q |
R |
D |
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PORTB7 |
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C |
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RL |
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WP |
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RP |
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WP: |
WRITE PORTB |
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MSTR |
WD: |
WRITE DDRB |
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SPE |
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RL: |
READ PORTB LATCH |
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SPI ClLOCK |
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RP: |
READ PORTB PIN |
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RD: |
READ DDRB |
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OUT |
SPE: |
SPI ENABLE |
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MSTR MASTER SELECT |
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SPI CLOCK |
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IN |
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