Материал: DOC1228

UART Control

UART0 I/O Data Register –

UDR0

UART1 I/O Data Register –

UDR1

UART0 Control and Status

Registers – UCSR0A

UART1 Control and Status

Registers – UCSR1A

For the slave MCUs, the mechanism appears slightly different for 8-bit and 9-bit reception mode. In 8-bit reception mode (CHR9n in UCSRnB cleared), the stop bit is one for an address byte and zero for a data byte. In 9-bit reception mode (CHR9n in UCSRnB set), the ninth bit is one for an address byte and zero for a data byte, whereas the stop bit is always high.

The following procedure should be used to exchange data in Multi-processor Communication Mode:

1.All slave MCUs are in Multi-processor Communication Mode (MPCMn in UCSRnA is set).

2.The master MCU sends an address byte and all slaves receive and read this byte. In the slave MCUs, the RXCn flag in UCSRnA will be set as normal.

3.Each slave MCU reads the UDRn register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA; otherwise, it waits for the next address byte.

4.For each received data byte, the receiving MCU will set the receive complete flag (RXCn in UCSRnA). In 8-bit mode, the receiving MCU will also generate a framing error (FEn in UCSRnA set), since the stop bit is zero. The other slave MCUs, which still have the MPCMn bit set, will ignore the data byte. In this case, the UDRn register and the RXCn, FEn, or flags will not be affected.

5.After the last byte has been transferred, the process repeats from step 2.

The UDRn register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDRn, the UART Receive Data register is read.

UART0 Control and Status

Registers – UCSR0B

UART1 Control and Status

Registers – UCSR1B

• Bit 0 – MPCM0/MPCM1: Multi-processor Communication Mode

This bit is used to enter Multi-processor Communication Mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCMn bit and starts data reception.

For a detailed description, see “Multi-processor Communication Mode”.

• Bit 7 – RXCIE0/RXCIE1: RX Complete Interrupt Enable

When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive Complete interrupt routine to be executed, provided that global interrupts are enabled.

• Bit 6 – TXCIE0/TXCIE1: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit Complete interrupt routine to be executed, provided that global interrupts are enabled.

• Bit 5 – UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART Data Register Empty interrupt routine to be executed, provided that global interrupts are enabled.

• Bit 4 – RXEN0/RXEN1: Receiver Enable

This bit enables the UART receiver when set (one). When the receiver is disabled, the TXCn, ORn and FEn status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.

• Bit 3 – TXEN0/TXEN1: Transmitter Enable

This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDRn has been completely transmitted.

• Bit 2 – CHR90/CHR91: 9-bit Characters

When this bit is set (one), transmitted and received characters are nine bits long, plus start and stop bits. The ninth bit is read and written by using the RXB8n and TXB8 bits in UCSRnB, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.

• Bit 1 – RXB80/RXB81: Receive Data Bit 8

When CHR9n is set (one), RXB8n is the ninth data bit of the received character.

• Bit 0 – TXB80/TXB81: Transmit Data Bit 8

When CHR9n is set (one), TXB8n is the ninth data bit in the character to be transmitted.

Baud Rate Generator

The baud rate generator is a frequency divider that generates baud rates according to the following equation:

BAUD fCK

= ---------------------------------

16(UBR + 1 )

•BAUD = Baud rate

•fCK= Crystal clock frequency

•UBR = Contents of the UBRRH and UBRR registers (0 - 4095)

•Note that this equation is not valid when the UART transmission speed is doubled. See “Double-speed Transmission” for a detailed description.

For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBR settings in Table 24. UBR values that yield an actual baud rate differing less than 2% from the target baud rate are boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance.

Table 24. UBR Settings at Various Crystal Frequencies