Материал: m013800e

Peak Time Counter 750-404/000-002

Technical data

The counter module also can be ordered as peak time counter with 750-404/000-002.

This description is only intended for hardware version X X X X 0 0 0 1- - - -. The serial number can be found on the right side of the module.

The counter begins processing with pulses at the CLOCK input. The changes from 0 V to 24 V are counted.

The counter counts up if the input U/D is set at 24 V. With an open circuit input or 0 V the counter counts backwards.

The two bottom contacts each include another output. These outputs are activated through bits in the control byte.

The counter module is able to run with all WAGOÇI/OÇSYSTEM bus-couplers (except for the economy type).

Organization of the inand output data:

The counter begins processing with pulses at the CLOCK input for a special time span. The time span is predefined as 10 s. The state of the counter is stored in the processs image until the next period. After the recording the counting starts again at 0.

The activation of the counting and the synchronisation with the SPS is made by a handshake in the control and status byte.

The end of thre counting period and thus the new process data is signaled by a toggel bit in the status byte.

The control byte has the following bits:

Control Byte

The status byte has the following bits:

Status Byte

Frequency Counter Module, 750-404/000-003

750-404

000-003

Technical Description

The counter module 750-404/000-003 measures the period of the 24 V DC input signal at the CLOCK terminal and converts it into a corresponding frequency value. The measurement is enabled if the GATE terminal is an open circuit input or 0V. To disable processing, the GATE input is to be set to 24 V DC.

The terminals O1 and O2 work as binary outputs. Each output can be activated via specific bits in the CONTROL byte.

The high states of the input and output channels are each indicated by a LED.

To recognize low frequency or near zero frequency signals, the maximum time between two data updates is parameterizable.

Functional description

The counter module acquires the time between one or more rising edges of the CLOCK input signal and calculates the frequency of the applied signal.

The calculation and process image update are initiated every 1st, every 4th or every 16th rising edge depending on the integration time selected via the CONTROL byte. The first detection of a rising edge starts the cyclic period measurement and cannot provide a valid frequency value. In this case the module will send 0xFFFFFFFFH for input information. The same input value is returned when a static high or static low signal is applied to the CLOCK input.

If there are no signal changes seen at the CLOCK input, the module can be forced to update the process image after defined parameterizable time spans. In this state the module will send the non valid value 0xFFFFFFFFH too.

The following figures illustrate a process data cycle.

Figure 3: Timing diagram for process data update sequence (integration time = 4 periods)