Материал: DOC1228

Sleep Modes

To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM1 bit in the MCUCR register and SM0 bit in the EMCUCR register select which sleep mode (Idle, Power-down or Power-save) will be activated by the SLEEP instruction (see Table 6). If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.

Timer/Counters

Timer/Counter

Prescalers

The ATmega161 provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz watch crystal, enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1 have individual prescaling selection from the same 10-bit prescaling timer. Timer/Counter2 has its own prescaler. Both these prescalers can be reset by setting the corresponding control bits in the Special Functions IO Register (SFIOR). Refer to page 39 for a detailed description. These Timer/Counters can either be used as a timer with an internal clock time base or as a counter with an external pin connection, which triggers the counting.

Figure 30. Prescaler for Timer/Counter0 and 1

For Timer/Counters 0 and 1, the four prescaled selections are: CK/8, CK/64, CK/256, and CK/1024, where CK is the oscillator clock. For the two Timer/Counters 0 and 1, CK, external source and stop can also be selected as clock sources. Setting the PSR10 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a prescaler reset will affect both Timer/Counters.

Special Function IO Register –

SFIOR

TIMER/COUNTER2 CLOCK SOURCE

TCK2

The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default connected to the main system clock (CK). By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the PD4(TOSC1) pin. This enables use of Timer/Counter2 as a Real-time Clock (RTC). When AS2 is set, pins PD4(TOSC1) and PD5(TOSC2) are disconnected from Port D. A crystal can then be connected between the PD4(TOSC1) and PD5(TOSC2) pins to serve as an independent clock source for Timer/Counter2. The oscillator is optimized for use with a 32.768 kHz crystal. Alternatively, an external clock signal can be applied to PD4(TOSC1). The frequency of this clock must be lower than one fourth of the CPU clock and not higher than 256 kHz. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.

8-bit Timer/Counters

T/C0 and T/C2

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is set (one), the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero.

Figure 32 shows the block diagram for Timer/Counter0. Figure 33 shows the block diagram for Timer/Counter2.

Figure 32. Timer/Counter0 Block Diagram

T/C0 OVER- T/C0 COMPARE

FLOW IRQ MATCH IRQ

8-BIT DATA BUS