Материал: sn74hc161

SN54HC161, SN74HC161 4 BIT SYNCHRONOUS BINARY COUNTERS

description/ordering information

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

ORDERING INFORMATION

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54HC161, SN74HC161

4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

description/ordering information (continued)

These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function for the ’HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.

†For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops.

Pin numbers shown are for the D, J, N, NS, PW, and W packages.

SN54HC161, SN74HC161

4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

logic symbol, each D/T flip-flop

D (Inverted Data) 3D

R (Inverted Reset) 4R

logic diagram, each D/T flip-flop (positive logic)

†The origins of LD and CK are shown in the logic diagram of the overall device.

SN54HC161, SN74HC161 4 BIT SYNCHRONOUS BINARY COUNTERS

SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003

typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:

1.Clear outputs to zero (asynchronous)

2.Preset to binary 12

3.Count to 13, 14, 15, 0, 1, and 2

4.Inhibit

CLR

LOAD

A

B

Data

Inputs

C

D

CLK

ENP

ENT

QA

Data QB

Outputs

QC

QD

RCO